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date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 1 sp6121 optimized for single input voltage - 3v to 5.5v high efficiency: greater than 95% possible accurate, 500khz fixed frequency operation fast transient response 500 a, i q (25 a in shutdown) internal, 0.4 v/ms, soft start circuit precision 1% reference resistor programmable output voltage lossless adjustable current limit with high side r ds(on) sensing 0% to 100% duty cycle range high side pmos switch negates need for external charge pump output over voltage protection hiccup mode current limit protection low voltage, synchronous step down pwm controller ideal for 2a to 10a, small footprint, dc-dc power converters applications supply bias for - dsp - microprocessor core - i/o & logic video cards board level supply in distributed power systems description the sp6121 is a fixed frequency, voltage mode, synchronous pwm controller designed to work from a single 5v or 3.3v input supply, providing excellent ac and dc regulation for high efficiency power conversion. the operating frequency is internally set at 500khz, permitting the use of small, surface mount inductors and capacitors. requiring only few external components, the sp6121 packaged in an 8-pin soic, is especially suited for low voltage applications where cost, small size and high efficiency are critical. with its low voltage capability and inherent 100% duty cycle operation, the sp6121 allows low dropout operation in the event of a low input supply voltage condition. q1 = fairchild fds6375 q2 = fairchild fds6690a ds = stmicroelectronics stps2l25bu l1 = panasonic etq-p6f1r6sfa c out = sanyo 4tpb470m v cc cb 3.3 f c in 47 f ceramic 6.3v i set 3.3v v in pdrv gnd comp sp6121 u1 v fb ndrv i sense cp 50pf rz 10k v out 1.8 h l1 c out 470 f x 2 rset 2.3k 1.9v 8a q1 cz 3.7nf q2 rv cc 5 ds r1 5.2k r2 10k features typical application circuit now available in lead free packaging 1 2 3 4 5 6 7 8 sp6121 8 pin nsoic comp v fb gnd pdrv ndrv i set i sense v cc
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 2 parameter min typ max units conditions quiescent current v cc supply current - 0.5 1.0 ma no switching v cc supply current (disabled) - 25 60 a comp = 0v error amplifier error amplifier transconductance 600 s comp sink current 15 35 65 av fb = 1.35v, comp=0.8v, no faults comp source current 15 35 65 av fb =1.15v, comp=1.8v comp output impedance 3 m ? v fb input bias current 100 na error amplifier reference initial accuracy 1.238 1.250 1.262 v trimmed with error amp in unity gain error amplifier reference over 1.225 1.250 1.275 v line, load and temperature oscillator & delay path internal oscillator frequency 440 500 560 khz maximum duty cycle 100 - - % comp = 2v minimum duty cycle - - 0 % comp = 0.8v minimum pdrv pulse width 100 ns v cc > 4.5v, ramp up comp voltage until pdrv starts switching current limit internal current limit threshold 125 160 195 mv v iset - v isense , t a = 25 c iset sink current 25 30 35 av iset =5v, t a = 25 c current limit threshold and 0.33 %/c iset temperature coefficient current limit time constant 15 s isense input bias current - - 100 na soft start, shutdown, uvlo internal soft start slew rate 0.4 v/ms measured at comp pin on the transition from shutdown internal soft start delay time 1.5 ms comp charging to pdrv switching comp discharge current 150 300 a comp = 0.5v, fault initiated comp clamp voltage 0.6 0.7 0.8 v v fb = 1.3v comp clamp current 100 a comp = 0.5v, v fb =1.15v electrical characteristics unless otherwise specified: 0 c < t a < 70 c, 3.0v < v cc < 5.5v, c comp = 22nf, c pdrv = c ndrv = 3.3nf, v fb = 1.25v, i set = i sense = v cc , gnd=0v these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ...................................................................................................... 7v all other pins ............................... -0.3v to v cc +0.3v peak output current < 10 s pdrv, ndrv ....................................................... 2a storage temperature ...................... -65 c to 150 c lead temperature (soldering, 10 sec) .......... 300 c esd rating ............................................... 2kv hbm absolute maximum ratings
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 3 pin description pin no. pin name description 1v cc positive input supply for the control circuitry and gate drivers. properly bypass this pin to gnd with a low esl/esr ceramic capacitor. 2 gnd ground pin. both power and control circuitry of the ic is referenced to this pin. 3v fb feedback voltage pin. it is the inverting input of the error amplifier and serves as the output voltage feedback point for the buck converter. the output voltage is sensed and can be adjusted through an external resistor divider. 4 comp output of the error amplifier. it is internally connected to the non-inverting input of the pwm comparator. a lead-lag network is typically connected to the comp pin to compensate the feedback loop in order to optimize the dynamic performance of the voltage mode control loop. sleep mode can be invoked by pulling the comp pin below 0.2v with an external open-drain or open-collector transistor. supply current is reduced to 25 a (typical) in shutdown. an internal 5 a pull-up ensures start-up. 5i sense current limit sense pin. connect this pin to the switching node at the junction between the two external power mosfet transistors. this pin monitors the voltage dropped across the r ds(on) of the high side p-channel mosfet while it is conducting. when this drop exceeds the sum of the voltage programmed through the i set pin plus the internal 160mv threshold, the overcurrent comparator sets the fault latch and termi- nates the output pulses. the controller stops switching and goes through a hiccup sequence. this prevents excessive power dissipation in the external power mosfets during an overload condition. an internal delay circuit prevents that very short and mild overload conditions, that could occur during a load transient, activate the current limit circuit. 6i set current limit threshold pin. an external resistor connected between this pin and the source of the high side p-channel mosfet adds to the internal current limit threshold of 160mv. if a current limit threshold in excess of 160mv is required, the external programming resistor can properly be chosen based on the internal 30 a pull down current available on the i set pin. both this 30 a current source and the 160mv built-in current limit threshold have a positive temperature coefficient to provide first order correction for the temperature coefficient of the external p-channel mosfet? r ds(on) . 7 ndrv high current driver output for the low side mosfet switch. it is always low if pdrv is low or during a fault. 8 pdrv high current driver output for the high side mosfet switch. it is always high if ndrv is high or during a fault. electrical characteristics unless otherwise specified: 0 c < t a < 70 c, 3.0v < v cc < 5.5v, c comp = 22nf, c pdrv = c ndrv = 3.3nf, v fb = 1.25v, i set = i sense = v cc , gnd=0v parameter min typ max units conditions soft start, shutdown, uvlo: continued shutdown threshold voltage 0.2 0.3 0.4 v measured at comp pin shutdown input pull-up current 5 a comp = 0.2v, measured at comp pin v cc start threshold 2.69 2.79 2.89 v v cc stop threshold 2.59 2.69 2.79 v v cc hysteresis - 100 - mv gate drivers pdrv rise time - 40 110 ns v cc > 4.5v pdrv fall time - 40 110 ns v cc > 4.5v ndrv rise time - 40 110 ns v cc > 4.5v pdrv fall time - 40 110 ns v cc > 4.5v pdrv to ndrv non-overlap time 80 ns v cc > 4.5v ndrv to pdrv non-overlap time 50 ns v cc > 4.5v
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 4 functional diagram + - - + - + synchronous driver pwm logic s q r reset dominant s q r iset v cc isense reference 5 4 3 6 1.25v uvlo f ault gnd 2 7 ndrv 8 driver enable reset dominant pwm comp f ault + - x 3.3 pdrv pdrv v cc 5 a 300mv shutdown gm error amp over current (gated s&h) 2.79v on 2.69v off 30 a (3300 ppm/ c) comp shutdown f = 500khz 750mv ramp 0.4v/ms softstart v fb comp 1 - + - + 1v 530mv (3300 ppm/ c) + - general overview the sp6121 is a constant frequency, voltage mode, synchronous pwm controller designed for low voltage, dc/dc step down converters. it is intended to provide complete control for a high power, high efficiency, precisely regulated output voltage from a highly integrated 8-pin solution. the internal free-running oscillator accurately sets the pwm frequency at 500khz without requiring any external elements and allows the use of physically small, low value external com- ponents without compromising performance. a transconductance amplifier is used for the error amplifier, which compares an attenuated sample of the output voltage with a precision reference voltage. the output of the error amplifier (comp), is compared to a 0.75v peak-to-peak ramp waveform to provide pwm control. the comp pin provides access to the output of the error amplifier and allows the use of external components to stabilize the voltage loop. high efficiency is obtained through the use of synchronous rectification. synchronous regula- tors replace the catch diode in the standard buck converter with a low r ds(on) n-channel mosfet switch allowing for significant effi- ciency improvements. the sp6121 includes two fast mosfet drivers with internal non-overlap circuitry and drives a complementary pair of power transistors, p-channel on the high side, and n-channel on the low side. the use of a p- channel high side device minimizes complexity and external component count by eliminating the need for a charge pump that would otherwise be required to fully enhance an n-channel de- vice. it also allows inherent 100% duty cycle for low dropout operation in the event of a low input supply voltage condition. the sp6121 includes an internal 0.4v/ms soft- start circuit that provides controlled ramp up of the output voltage, preventing overshoot and inrush current at power up. current limiting is implemented by monitoring the voltage drop across the r ds(on) of the high side p-channel mosfet while it is conducting, thereby eliminating the need for an external sense resistor. the over-current comparator has a built-in threshold of 160mv that can be pro- grammed to higher values using a single exter- nal resistor, connected to the i set pin, whose theory of operation
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 5 value is selected to match the mosfet charac- teristics. when the over-current threshold is exceeded, the over-current comparator sets the fault latch and terminates the output pulses. the controller stops switching and goes through a hiccup sequence. this prevents excessive power dissipation in the external power mosfets during an overload condition. an internal delay circuit prevents that very short and mild over- load conditions, that could occur during a load transient, activate the current limit circuit. a low power sleep mode can be invoked in the sp6121 by externally forcing the comp pin below 0.3v. quiescent supply current in sleep mode is typically less than 25 a. an internal 5 a pull-up current at the comp pin brings the sp6121 out of shutdown mode. the sp6121 also includes under-voltage lock- out and over-voltage protection. output over- voltage protection is achieved by turning off the high side switch, and turning on the low side n- channel mosfet full time. enable low quiescent mode or ?leep mode?is initi- ated by pulling the comp pin below 0.3v with an external open-drain or open-collector tran- sistor. supply current is reduced to 25 a (typi- cal) in shutdown. on power-up, assuming that v cc has exceeded the uvlo start threshold (2.79v), an internal 5 a pull-up current at the comp pin brings the sp6121 out of shutdown mode and ensures start-up. during normal oper- ating conditions and in absence of a fault, an internal clamp prevents the comp pin from swinging below 0.6v. this guarantees that dur- ing mild transient conditions, due either to line or load variations, the sp6121 does not enter shutdown unless it is externally activated. during sleep mode, the high side and low side mosfets are turned off and the internal soft start voltage is held low. uvlo assuming that there is not shutdown condition present, then the voltage on the v cc pin deter- mines operation of the sp6121. as v cc rises, the uvlo block monitors v cc and keeps the high side and low side mosfets off and the internal ss voltage low until v cc reaches 2.79v. if no faults are present, the sp6121 will initiate a soft start when v cc exceeds 2.79v. hysteresis (about 100mv) in the uvlo com- parator provides noise immunity at start-up. soft start soft start is required on step-down controllers to prevent excess inrush current through the power train during start-up. typically this is managed by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up either the error amp reference or the error amp output (comp). the control loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady-state duty cycle as the output voltage increases to its regu- lated value. as a result of controlling the induc- tor volt*second product during startup, inrush current is also controlled. in the sp6121 the duration of the soft-start is controlled by an internal timing circuit that provides a 0.4v/ms slew-rate, which is used during start-up and over-current to set the hic- cup time. the sp6121 implements soft-start by ramping up the error amplifier reference voltage providing a controlled slew-rate of the output voltage, thereby preventing overshoot and in- rush current at power up. the presence of the output capacitor creates extra current draw during startup. simply stated, dv out /dt requires an average sustained current in the output capacitor and this current must be considered while calculating peak inrush cur- rent and over current thresholds. an approxi- mate expression to determine the excess inrush current due to the dv out /dt of the output capaci- tor c out is: ic out = c out *(0.4 v/ms) * v out 1.25 as figure 1 shows, the ss voltage controls a variety of signals. first, provided all the exter- nal fault conditions are removed, an internal 5 a pull-up at the comp pin brings the sp6121 out of shutdown mode. the internal timing circuit is then activated and controls the ramp- up of the error amp reference voltage. the comp pin is pulled to 0.7v by the internal theory of operation
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 6 clamp and then gradually charges preventing the error amplifier from forcing the loop to maximum duty cycle. as the comp voltage crosses about 1v (valley voltage of the pwm ramp), the driver begins to switch the high side mosfet with narrow pulses in an effort to keep the converter output regulated . the sp6121 operates at low duty cycle as the comp voltage increases above 1v. as the error amp reference ramps upward, the driver pulses widen until a steady state value is reached and the output voltage is regulated to the final value ending the soft start charge cycle. hiccup mode when the converter enters a fault mode, the sp6121 holds the high side and low side mosfets off for a finite period of time. pro- vided that the sp6121 is enabled, this time is set by the internal charge of the ss capacitor. in the event of an over-current condition, the current sense comparator sets the fault latch, which in turn discharge the internal ss capacitor, the comp pin and holds the output drivers off. during this condition, the sp6121 stays off for the time it takes to discharge the comp pin down below the 0.3v shutdown threshold. as soon as the comp pin reaches 0.3v, the fault latch is reset and the sp6121 is allowed to attempt restart just like during a normal soft start cycle. the comp pin has to charge back to 1v before any output switching can take place. at this point, the regulator attempts to restart nor- mally by delivering short gate pulses to the output switches. if the over-current condition persists, the regulator will be kept off for the total time that it takes to charge the internal soft- start capacitor to within 1v from the input supply voltage v cc plus the time required by the comp voltage to cross the 1v threshold. this total time is typically several milli-seconds and minimizes thermal stress to the regulator com- ponents as the over-current condition persists. the waveforms that describe the hiccup mode operation are shown in figure 2. 160 mv 3 v 0 v 1.0 v 0v v (vcc) v (iset) -v (isense) pdrv volt age time 0 v 0.3 v comp volt age figure 2. sp6121 hiccup mode waveforms dvss/dt = 0.4v/ms 1.25v i(l) time 0.3 v 0.7 v 1 v 0 v v out = v (ref) * (1+r1/r2) comp internal ss 0 v swn v oltage v oltage faul t current inductor 0 a v oltage reference error amp 0 v v(v cc ) 0 v v(v cc ) figure 1. sp6121 soft start waveforms theory of operation
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 7 over current protection over current protection on the sp6121 is imple- mented through detection of an excess voltage condition across the high side pmos switch during conduction. this is typically referred to as high side r ds(on) detection and eliminates the need of an external sense resistor. the over current comparator charges an internal sam- pling capacitor each time v (iset) - v (isense) exceeds the 160mv (typ) internal threshold and the pdrv voltage is low. the discharge/charge current ratio on the sampling capacitor is about 2%. therefore, provided that the over current condition persists, the capacitor voltage will be pumped up during each time pdrv switches low. this voltage will trigger an over current condition upon reaching a cmos inverter thresh- old. there are many advantages to this ap- proach. first, the filtering action of the gated s/ h scheme protects against false and undesirable triggering that could occur during a minor tran- sient overload condition or supply line noise. furthermore, the total amount of time to trigger the fault depends on the on-time of the pmos switch. ten, 1 s pulses are equivalent to twenty, 500ns pulses or one, 10 s pulse, however, de- pending on the period, each scenario takes a different amount of total time to trigger a fault. therefore, the fault becomes an indicator of average power in the pmos switch. although the 160 mv internal threshold is fixed, the overall r ds(on) detection voltage can be increased by placing a resistor from i set to the source of the pmos. a 30 a sink current pro- grams the additional voltage. in order for the current limit circuit to operate properly and accurately, the i set and i sense pins must be kelvin connected to the high side pmos? source and drain pins. the 160mv threshold and 30 a i set current have 3300 ppm/ c temperature coefficients in an effort to first order match the thermal charac- teristics of the r ds(on) of the pmos switch. it assumed that the sp6121 will be used in com- pact designs where there is a high amount of thermal coupling between the pmos and the controller. output drivers the sp6121, unlike some other bipolar control- ler ic?, incorporates gate drivers with rail-to- rail swing that help prevent spurious turn on due to capacitive coupling. the driver stage consists of one high side pmos, 4 ? driver, pdrv, and one low side, 4 ? , nfet driver, ndrv, opti- mized for driving external power mosfet? in a synchronous buck topology. the output driv- ers also provide gate drive non-overlap mecha- nism that provides a dead time between pdrv and ndrv transitions to avoid potential shoot- through problems in the external mosfet?. figure 3 shows typical waveforms for the output drivers. as with all synchronous designs, care must be taken to ensure that the mosfets are properly chosen for non-overlap time, enhance- ment gate drive voltage, ?n?resistance r ds(on) , reverse transfer capacitance crss, input voltage and maximum output current. time ndrv pdrv v(v cc ) - v(diode) v ~ 0 v v oltage swn v oltage v(v cc ) 0 v 0 v v(v cc =v in ) v oltage vcc-2 v non-overlap 2 v rise time 10 % 90 % f all time ndrv(pdrv) pdrv(ndrv) 5 v 10 % 90 % 5 v gate driver test conditions figure 3. sp6121 output driver waveforms. theory of operation
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 8 inductor selection there are many factors to consider in selecting the inductor including cost, efficiency, size and emi. in a typical sp6121 circuit, the inductor is chosen primarily for value, saturation current and dc resistance. increasing the inductor value will decrease output voltage ripple, but degrade transient response. low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and more output capacitance to smooth out the larger ripple current. the induc- tor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. a good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. the switching frequency and the inductor oper- ating point determine the inductor value as fol- lows: (max) (max) (max) ) ( out r s in out in out i k f v v v v l ? = where; f s = switching frequency k r = ratio of the peak to peak inductor ripple current to the maximum output current the peak to peak inductor ripple current is: l f v v v v i s in out in out pp (max) (max) ) ( ? = once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency require- ments. the core material must be large enough not to saturate at the peak inductor current 2 (max) pp out peak i i i + = and provide low core loss at the high switching frequency. low cost powdered iron cores have a gradual saturation characteristic but can intro- duce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the induc- tance dropping sharply when the peak design current is exceeded. nevertheless, they are pre- ferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. the power dissipated in the inductor is equal to the sum of the core and copper losses. to mini- mize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. core losses have a more significant contribution at low output cur- rent where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. core loss information is usually available from the magnetic vendor. the copper loss in the inductor can be calculated using the following equation: winding rms l cu l r i p 2 ) ( ) ( = where i l(rms) is the rms inductor current that can be calculated as follows: i l(rms) = i out(max) 1 + 1 ( i pp ) 2 3 i out(max) output capacitor selection the required esr (equivalent series resis- tance) and capacitance drive the selection of the type and quantity of the output capacitors. the esr must be small enough that both the resis- tive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. during an output load transient, the output capacitor must supply all the addi- tional current demanded by the load until the sp6121 adjusts the inductor current to the new value. therefore the capacitance must be large enough so that the output voltage is held up application information
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 9 panasonic offers the sp series of specialty poly- mer aluminum electrolytic surface mount ca- pacitors. these capacitors have a lower esr than tantalum capacitors, reducing the total num- ber of capacitance required for a given transient response. input capacitor selection the input capacitor should be selected for ripple current rating, capacitance and voltage rating. the input capacitor must meet the ripple current requirement imposed by the switching current. in continuous conduction mode, the source cur- rent of the high-side mosfet is approximately a square wave of duty cycle v out / v in . most of this current is supplied by the input bypass capacitors. the rms value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: i cin(rms) = i out(max) d(1 - d) the worse case occurs when the duty cycle d is 50% and gives an rms current value equal to iout/2. select input capacitors with adequate ripple current rating to ensure reliable opera- tion. the power dissipated in the input capacitor is: ) ( 2 ) ( cin esr rms cin cin r i p = this can become a significant part of power losses in a converter and reduce the overall energy transfer efficiency. the input voltage ripple primarily depends on the input capacitor esr and capacitance. ignor- ing the inductor ripple current, the input voltage ripple can be determined by: ? v in = i out(max) r esr(cin) + i out(max) v out (v in - v out ) f s c in v in 2 the capacitor type suitable for the output ca- pacitors can also be used for the input capaci- tors. however, exercise extra caution when tan- talum capacitors are considered. tantalum ca- pacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power while the inductor current ramps up or down to the value corresponding to the new load current. additionally, the esr in the output capacitor causes a step in the output voltage equal to the esr value multiplied by the change in load current. because of the fast transient response provided by the sp6121 when exposed to output load transient, the output capacitor is typically chosen for esr , not for capacitance value. the output capacitor? esr, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. the maxi- mum allowable esr required to maintain a specified output voltage ripple can be calculated by: pp out esr i v r ? where; ? v out = peak to peak output voltage ripple i pp = peak to peak inductor ripple current the total output ripple is a combination of the esr and the output capacitance value and can be calculated as follows: ? v out = ( i pp (1 ?d) ) 2 + (i pp r esr ) 2 c out f s where; d = duty cycle equal to v out /v in c out = output capacitance value recommended capacitors that can be used ef- fectively in sp6121 applications are: low-esr aluminum electrolytic capacitors, os-con ca- pacitors that provide a very high performance/ size ratio for electrolytic capacitors and low- esr tantalum capacitors. avx tps series and kemet t510 surface mount capacitors are popu- lar tantalum capacitors that work well in sp6121 applications. poscap from sanyo is a solid electrolytic chip capacitor that has low esr and high capacitance. for the same esr value, poscap has lower profile compared with tan- talum capacitor. applications information
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 10 supplies are connected ?ive?to low impedance power sources. certain tantalum capacitors, such as avx tps series, are surge tested. for ge- neric tantalum capacitors, use 2:1 voltage derat- ing to protect the input capacitors from surge fall-out. mosfet selection the sp6121 drives a pmos mosfet on the high side and an nmos mosfet synchronous rectifier on the low side. using a pmos switch on the high side negates the need for an external charge pump and simplifies the application cir- cuit. the losses associated with mosfets can be divided into conduction and switching losses. conduction losses are related to the on resis- tance of mosfets, and increase with the load current. switching losses occur on each on/off transition when the mosfets experience both high current and voltage. since the bottom mosfet switches current from/to a paralleled diode (either its own body diode or a schottky diode), the voltage across the mosfet is no more than 1v during switching transition. as a result, its switching losses are negligible. the switching losses are difficult to quantify due to all the variables affecting turn on/off time. how- ever, making the assumption that the turn on and turn off transition times are equal, the transition time can be approximated by: t t = c iss v in , i g where; c iss is the pmos? input capacitance, or the sum of the gate-to-source capacitance, c gs , and the drain-to-gate capacitance, c gd . this param- eter can be directly obtained from the mosfet? data sheet i g is the gate drive current provided by the sp6121 (approximately 1a at v in =5v) and v in is the input supply voltage. therefore an approximate expression for the switching losses associated with the high side mosfet can be given as: p sh(max) = (v in(max) + v f )i out(max) t t f s , where; t t = the switching transition time v f = free wheeling diode drop switching losses need to be taken into account for high switching frequency, since they are directly proportional to switching frequency. the conduction losses associated with top and bottom mosfets are determined by p ch(max) = r ds(on) i out(max) 2 d p cl(max) = r ds(on) i out(max) 2 (1 - d), where; p ch(max) = conduction losses of the high side mosfet p cl(max) = conduction losses of the low side mosfet r ds(on) = drain to source on resistance. the total power losses of the top mosfet are the sum of switching and conduction losses. for synchronous buck converters of efficiency over 90%, allow no more than 4% power losses for high or low side mosfets. for input voltages of 3.3v and 5v, conduction losses often domi- nate switching losses. therefore, lowering the r ds(on) of the mosfets always improves efficiency even though it gives rise to higher switching losses due to increased c iss . total gate charge is the charge required to turn the mosfets on and off under the specified operating conditions (v gs and v ds ). the gate charge is provided by the sp6121 gate drive circuitry. (at 500khz switching frequency, the gate charge is the dominant source of power dissipation in the sp6121.) at low output levels, this power dissipation is noticeable as a reduc- tion in efficiency. the average current required to drive the high side and low side mosfets is: i g(av) = q gh f s + q gl f s , where; q gh = gate charge of pmos q gl = gate charge of nmos considering that the gate charge current comes from the input supply voltage vin, the power dissipated in the sp6121 due to the gate drive is: p gate drive = v in i g(av) r ds(on) varies greatly with the gate driver volt- age. the mosfet vendors often specify r ds(on) on multiple gate to source voltages (v gs ), as applications information
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 11 well as provide typical curve of r ds(on) versus v gs . for 5v input, use the r ds(on) specified at 4.5v v gs . at the time of this publication, ven- dors, such as fairchild, siliconix and interna- tional rectifier, have started to specify r ds(on) at v gs less than 3v. this has provided necessary data for designs in which these mosfets are driven with 3.3v and made it possible to use sp6121 in 3.3v only applications. thermal calculation must be conducted to en- sure the mosfet can handle the maximum load current. the junction temperature of the mosfet, determined as follows, must stay below the maximum rating. ja mo sfet a j r p t t (max) (max) ( max) + = , where; t a(max) = maximum ambient temperature p mosfet(max) = maximum power dissipation of the mosfet r ja = junction to ambient thermal resistance. r ja of the device depends greatly on the board layout, as well as device package. significant thermal improvement can be achieved in the maximum power dissipation through the proper design of copper mounting pads on the circuit board. for example, in a so-8 package, plac- ing two 0.04 square inches copper pad di- rectly under the package, without occupying additional board space, can increase the maxi- mum power from approximately 1 to 1.2w. for dpak package, enlarging the tap mount- ing pad to 1 square inches reduces the r ja from 96 c/w to 40 c/w. schottky diode selection when paralleled with the bottom mosfet, an optional schottky diode can improve efficiency and reduce noise. without this schottky diode, the body diode of the bottom mosfet con- ducts the current during the non-overlap time when both mosfets are turned off. unfortu- nately, the body diode has high forward voltage and reverse recovery problem. the reverse re- covery of the body diode causes additional switching noises when the diode turns off. the schottky diode alleviates this noise and addi- tionally improves efficiency thanks to its low forward voltage. the reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. the power dissipation of the schottky diode is determined by p diode = 2v f i out t nol f s where; t nol = non-overlap time between pdrv and ndrv. v f = forward voltage of the schottky diode. sp6121 c2 c1 r1 comp figure 4. the rc network connected to the comp pin provides a pole and a zero to control loop. loop compensation design the goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/dec. the sp6121 has a trans-conductance error amplifier and re- quires the compensation network to be con- nected between the comp pin and ground, as shown in figure 4. the first step of compensation design is to pick the loop crossover frequency. high crossover frequency is desirable for fast transient response, but often jeopardize the system stability. cross- over frequency should be higher than the esr zero but less than 1/5 of the switching fre- quency. the esr zero is contributed by the esr applications information
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 12 associated with the output capacitors and can be determined by f z(esr) = 1 2 c out r esr crossover frequency of 20khz is a sound first try if low esr tantalum capacitors or poscaps are used at the output. the next step is to calcu- late the complex conjugate poles contributed by the lc output filter, f p(lc) = 1 2 lc out the open loop gain of the whole system can be divided into the gain of the error amplifier, pwm modulator, buck converter, and feedback resistor divider. in order to crossover at the selected frequency fco, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. in the rc network shown in figure 4, the product of r1 and the error amplifier transconductance determines this gain. therefore, r1 can be deter- mined from the following equation that takes into account the typical error amplifier transconductance, reference voltage and pwm ramp built into the sp6121. r1 = 975v out f co f z (esr) v in f p(lc) 2 in figure 4, r1 and c1 provides a zero f z1 which needs to be placed at or below f p(lc) . if f z1 is made equal to f p(lc) for convenience, the value of c1 can be calculated as c1 = 1 2 f p(lc) r 1 the optional c2 generates a pole f p1 with r1 to cut down high frequency noise for reliable op- eration. this pole should be placed one decade higher than the crossover frequency to avoid erosion of phase margin. therefore, the value of the c2 can be derived from c2 = 1 20 f co r 1 figure 5 illustrates the overall loop frequency response and frequency of each pole and zero. to fine-tune the compensation, it is necessary to physically measure the frequency response us- ing a network analyzer. gain -20db/dec -40db/dec -20db/dec -20db/dec -20db/dec error amplifier loop f f figure 5. frequency response of a stable system and its error amplifier. overcurrent protection over current protection on the sp6121 is imple- mented through detection of an excess voltage condition across the high side pmos switch during conduction. this is typically referred to as high side r ds(on) detection. by using the r ds(on) of q1 to measure the output current, the current limit circuit eliminates the sense resistor that would otherwise be required and the corre- sponding loss associated with it. this improves the overall efficiency and reduces the number of components in the power path benefiting size and cost. r ds(on) sensing is by default inaccu- rate and is primarily meant to protect the power supply during a fault condition. the overcurrent trip point will vary from unit to unit as the r ds(on) of q1 varies. the sp6121 provides a built-in 160mv threshold between the i set and i sense pins. if a current limit threshold in excess of 160mv is required, an external programming resistor, r set can be added between i set pin and v in as shown in figure 6. applications information
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 13 figure 7(a) a voltage divider connected to the v fb pin programs the output voltage. (b) a simple circuit using one external voltage reference programs the output voltages less than 1.25v. ab v ref v fb v fb v out < 1.25v v out > 1.25v sp6121 sp6121 r1 r2 r1 r2 r3 c in i set v in pdrv sp6121 ndrv i sense v out l1 c out rset q1 q2 + - + - 160mv 30 a figure 6. current limit setting the value of r set can be properly chosen based on the desired current limit point i max and the internal 30 a pull down current available on the i set pin according to the following expression: r set = i max r ds(on) - 160mv i set where, i set = 30 a (typ) sink current from the i set pin. kelvin-sense connections should be made di- rectly at the drain and source of q1. the r ds(on) sensing scheme implemented in the sp6121 provides two additional features that enhance the performance of the overcurrent function. first, an internal sample and hold filter connected after the main current-sense com- parator, prevents that noise spikes or very short and mild overload conditions, that could occur during a load transient, spuriously activate the c urrent limit circuitry. this typically eliminates the need of using any external filtering that would be otherwise required. additionally, since the r ds(on) has a positive temperature coeffi cient, both the 30 a sink current present at the i set pin a nd the 160mv built-in current limit threshold have been designed with a positive temperature coefficient of about 0.33%/c to provide first order correction for current limit versus temperature. this compensation relies on the high amount of thermal coupling that typically exists between the high side switch q1 and the sp6121 due to the compact size of the power supply. with this first order compensation, the current limit trip point does not need to be set to an increased level at room temperature to guarantee a desired output current level at higher temperatures. output voltage program as shown in figure 7(a), the voltage divider connecting to the v fb pin programs the output voltage according to v out = 1.25 ( 1 + r1 ) r2 where 1.25v is the internal reference voltage. select r2 in the range of 10k to 100k, and r1 can be calculated using r1 = r2(v out - 1.25) 1.25 for output voltage less than 1.25v, a simple circuit shown in figure 7(b) can be used in which v ref is an external voltage reference greater than 1.25v. for simplicity, use the same resistor value for r1 and r2, then r3 is deter- mined as follows, r3 = (v ref - 1.25)r1 2.5v - v out applications information
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 14 pcb layout plays a critical role in proper func- tion of the converters and emi control. in switch mode power supplies, loops carrying high di/dt give rise to emi and ground bounces. the goal of layout optimization is to identify these loops and minimize them. it is also crucial on how to connect the controller ground such that its op- eration is not affected by noise. the following guideline should be followed to ensure proper operation. 1. a ground plane is recommended for minimiz- ing noises, copper losses and maximizing heat dissipation. 2. begin the layout by placing the power compo- nents first. orient the power circuitry to achieve a clean power flow path. if possible make all the connections on one side of the pcb with wide, copper filled areas. 3. connect the ground of feedback divider and compensation components directly to the gnd pin of the ic using a dedicated ground trace. then connect this pin as close as possible to the ground of the output capacitor. 4. the v cc bypass capacitor should be right next to the v cc and gnd pins. 5. the trace connecting the feedback resistors to the output should be short, direct and far away from the switch node, and switching compo- nents. 6. minimize the trace between pdrv/ndrv and the gates of the mosfets to reduce the impedance driving the mosfets. this is espe- cially important for the bottom mosfet that tends to turn on through its miller capacitor when the switch node swings high. 7. minimize the loop composed of input capaci- tors, top/bottom mosfets and schottky diode. this loop carries high di/dt current. also in- crease the trace width to reduce copper losses. 8. maximize the trace width of the loop connect- ing the inductor, output capacitors, schottky diode and bottom mosfet. 9. i set and i sense connections to q1 for current limiting must be make using kelvin connec- tions. layout guideline
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 15 package: 8 pin nsoic a a1 a2 side view seating plane section b-b with plating symbol min nom max a 1.35 - 1.75 a1 0.1 - 0.25 a2 1.25 - 1.65 b 0.31 - 0.51 c 0.17 - 0.24 d e e1 e l 0.4 - 1.27 l1 l2 ?0o-8o ?1 5o - 15o note: dimensions in (mm) 8 pin nsoic jedec mo-012 (aa) variation 4.90 bsc 6.00 bsc 3.90 bsc 1.27 bsc 1.04 ref 0.25 bsc gauge plane l1 l 1 seating plane l2 view c to p view b see view c b b e e/2 e1 index area (d/2 x e1/2) e1/2 d 1 e c base metal b
date: 11/29/04 sp6121 low voltage, synchronous step down pwm controller ?copyright 2004 sipex corporation 16 corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 ordering information part number operating temperature range package type sp6121cn ............................................... 0?c to +70?c ........................................... 8-pin nsoic sp6121cn/tr ......................................... 0?c to +70?c .......................................... 8-pin nsoic available in lead free packaging. to order add "-l" suffix to part number. example: sp6121cn/tr = standard; SP6121CN-L/tr = lead free /tr = tape and reel pack quantity is 2,500 for nsoic.
datasheet appendix & web link information ? 2007 sipex corporation for further assistance: email: sipexsupport@sipex.com www support page: http://www.sipex.com/content.aspx?p=support sipex application notes: http://www.sipex.com/applicationnotes.aspx product change notices: http://www.sipex.com/content.aspx?p=pcn sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca95035 tel: (408) 934-7500 fax: (408) 935-7600 sipex corporation reserves the right to make change s to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither do es it convey any license under its patent rights no r the rights of others. the following sections contain information which is more changeable in nature and is therefore generated as appendices. 1) package outline drawings 2) ordering information if available: 3) frequently asked questions 4) evaluation board manuals 5) reliability reports 6) product characterization reports 7) application notes for this product 8) design solutions for this product solved by tm solved by tm appendix and web link information
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nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 1 introduction the sp6121 is a 500khz pwm controller wit h input voltage range from 3.0v to 5.5v. this is ideal for dra wing power out of a one-cell li ion battery which varies from 3.4v to 4.3v. the requirement for this application is to provide a maximum 1.5a regulated current into a k2 lumileds luxeon? led. the topology used here is a ?non-inverti ng cuk boost/buck?. the circuit will also use an external amplifier for converting the current sensing (i led ) into the appropriate voltage level requested by the sp6121 to regulate properly. principle of operation the simplified form of a boost buck conver ter is shown below. the converter can be separated into two cells, a boost cell made out of s1 and l1 and a buck cell around s2 and l2. s1 and s2 are controlled out of phase. phase 1 is s1 closed li ion battery [3.4v ? 4.3v] luxeon? k2 1.5a max [3.4 < vf > 4.0v] high efficiency buck/boost converter w/ output current regulation li ion battery [3.4v ? 4.3v] sp6121 pwm controlle r current sensing amplifier boost / buck cells over voltage protection k2 solved by tm application note anp13 applying the sp6121 as a synchronousbuck-boost 1.5a k2 luxeon driver
nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 2 and s2 open (on time). phase 2 is s1 open and s2 closed (off time). the duty cycle will be t on /t off . c1 is an energy transfer c apacitor and is used to provide a positive voltage on v2 so the buck cell can regulate t he appropriate v out . during on time, i 1 current is stored into l1 and al so provided to l2 through c1. during off time, v2 equals gnd and any remain ing current in l2 still delivers to the load. at the same time, the voltage acro ss c1 is equal to v1 and so becomes negative as current is still flowing across l1. v c1 = (v2-v1) and is positive. during the following on-time, this v c1 is added on top of v in and so generates a positive voltage v2 to the buck cell (v2 = vin + vc1). figure 1 the duty cycle of this converter will be : v out / v in = d / (1-d) or d = _______1 _______ [ ( v in /v out ) + 1] so typically, if v in equals v out the duty cycle will be 50%. design considerations our need here is to power a luxeon k2 at 1.5a from a one cell li i on battery pack. the k2 is an ultra-bri ght led that has a vf from 3.6 to 4.3v depending on if and temperature. the battery will have a voltage from 3.4v to 4.2v. also depending on charge level, battery output impedance can vary and so induce a loss depending on output current. due to these conditions, a step up/step down topology is definitely required to get a constant current into the led regardless of v1 v2 v in v out
nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 3 the battery voltage. the converter will automatically adjust its duty cycle depending on these factors. the below gr aph shows the area which will be used. note that the duty cycle will stay around 50%. this value will be used as a reference for calculating the external components. 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 d : duty cycle vo / vin boost cell buck cell current sensing current sensing amplifier led disconnect overvoltage protection sp6121 buck-boost a pp lication schematic
nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 4 schematic description sp6121 500khz synchronous pwm controller lmv321 low voltage op amp for current sensing drq125-47 dual winding coil 4.7h t1 pmos transistor t2 nmos transistor d2 zener diode for ovp component options the first component to choose is the coil. l1 and l2 will be chosen so they have the same value, in order to be able to use a dual winding coil (two coils on the same core). this kind of coil is usually used in a sepic converter and is now a very common product. the advantages to us ing a spiral winding coil versus two single coils are reduced footprint (the pack age is typically the same as a single coil) and reduced current ripple due to internal coupling. if we state that duty cycle will be 50% (v in = v out ), we can make the assumption that the ac current going through l1 and l2 are the same. from the buck cell we have: ut v v dt di l vl o 2 2 2 ? = = (v2 = secondary switch node voltage) 1 2 2 ? ? = d f ripple i l v v out out (ripple=ripple ratio, f=freq, d=duty cycle) 1 2 2 ? ? = d f i ripple v v l out out in this case, as we are powering an led, we can set the current ripple to be high as it does not matter for the led lightin g performance. also this will let us reduce the coil value and reduce pcb area . in this topology, v2 (secondary switch node voltage), is always equal to v out + v in regardless of the input and output voltages. v in = 3.8v (average voltage of the battery) v out = 3.8v (average voltage of the k2 led) v2 = v in + v out = 7.6v ripple = 40% i out = 1.5a f = 500khz d = 50%
nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 5 1 5 . 0 500000 5 . 1 4 . 0 8 . 3 6 . 7 2 ? ? = l = 6.33h as we are using a dual winding coil we choose a 4.7h inductor. using a coupled coil allows for this because the ac current is reduced considerably due to internal coupling between the 2 inductors. transistor t1 is a p-channel fet. it is directly controlled by the sp6121 pwm controller. it must be able to saturate its v gs with the minimum input voltage of 3.4v. a typical 2.5v trench mosfet is well suited for this environment. t2 is the same but is an n channel fet -- the v gs requirement is the same. max v ds for both is 20v; id max is approximately equal to i led max + 50% = 2.3a. as the duty cycle can get higher when the battery is low, the current in the primary cell will increase a bit and then t1 will need to handle mo re current. doubling the output current is a good estimate for calibrating the pmos transistor. c1 is the energy transfer capacitor. th is component does not transfer any dc energy but only ac. so in order to minimi ze the loss we ar e choosing a 10f ceramic capacitor with low esr. c out is very important as it st ores all the energy during t off , and so maintains the output voltage. this is a 100f tantalum capacitor . a lower value may not be suitable to start the converter at full load with a low voltage battery. the current regulation is done by sensing the led current via r4. as it is a 100m ? resistor, v r4 = 0.1 x i led . the converter is made to regulate 1.5a into the led. the voltage across r4 will then be 150mv. as the feedback voltage of the pwm controller is 1.25v, we will need an amplifier made out of an lmv321. this amplifier is a simple non-inverting ci rcuit with gain of 1.25 / 0.15 = 8.33. in this case gain is: 3 2 1 r r + in order to have a safe design, we need to include overvoltage protection to clamp the output voltage in case of a burned led. this is due to the fact that under a current-regulation architecture, an open circuit load is viewed by the controller as 0 volts v out , and so it will infinitely try to increase its value. the ovp circuit is made out of a simple zener diode. we choose its voltage so it is more than the maximum vf of the k2 led and less than the maximum voltage that transistors can support. in our case we took a zener diode of 5.1v. in order to prevent short-circuiting of the low impedance output of the lmv321, a 10k ? resistor (r5) is inserted between its output and the fb input of the sp6121.
nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 6 circuit performance start up in order to soft-start the converter, use a 1f capacitor between the comp pin and gnd. the comp pin is actu ally the internal output of the error amplifier. this high capacitance value will ac t as a local integrator, slowing down any fast variation due to star t up or transients. start up v in =5.0v start up v in =3.3v led efficiency vs output load 50 60 70 80 90 100 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 output load (ma) efficiency (%) iout=1.0a iout=1.5a v in v out v sense i in 1a/div v in v out v sense i in 1a/div
nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 7 experimental data i out = 1.0a v in i in v out v sense i out ripple effi effi to led (v) (a) (v) (mv) (ma) (mv) (%) (%) 5.0 0.924 3.796 154.8 1032 22 84.8 81.3 4.5 0.999 3.794 154.8 1032 22 87.1 83.5 4.2 1.080 3.793 154.8 1032 22 86.3 82.8 4.0 1.138 3.792 154.7 1031 20 85.9 82.4 3.8 1.204 3.791 154.5 1030 20 85.3 81.9 3.6 1.279 3.79 154.3 1029 20 84.7 81.2 3.4 1.367 3.789 154.1 1027 20 83.8 80.3 3.2 1.471 3.788 153.9 1026 20 82.6 79.2 3.0 1.601 3.788 153.8 1025 20 80.9 77.6 i out = 1.5a v in i in v out v sense i out ripple effi effi to led (v) (a) (v) (mv) (ma) (mv) (%) (%) 5.0 1.385 3.940 150.8 1508 20 85.8 82.5 4.5 1.530 3.940 150.2 1502 20 86.0 82.7 4.2 1.649 3.930 149.7 1497 23 84.9 81.7 4.0 1.740 3.925 149.4 1494 25 84.3 81.0 3.8 1.845 3.920 149.3 1493 25 83.5 80.3 3.6 1.972 3.918 149.3 1493 25 82.4 79.3 3.4 2.121 3.918 149.6 1496 23 81.3 78.2 3.2 2.310 3.918 149.9 1499 23 79.5 76.4 3.0 2.544 3.919 150.5 1505 22 77.3 74.3
nov 28 06 appnote: sp6121 as a synchronous buck-boost led driver ? 2006 sipex corporation page 8 circuit waveforms v in v out ripple noise, v in =5.0v ripple noise, v in =3.3v pdrv ndrv switching behavior, v in =3.3v v sense i l2 1a/div i l1 1a /div switching behavior, v in =5.0v
mar29-06 sp6121 buck/boost circuit for led driver up to 1.5a copyright ?2006 page 1 of 4 sipex corporation sp6121 buck/boost circuit for led driver up to 1.5a date: march 29, 2006 designed by: brian kennedy part number: sp6121cn application description: provide high output current from 3vin to 5vin electrical requirements: input voltage 3.0v ? 5.0v output voltage ~3.9v (led vf + 0.15v vref) output current up to 1.5a circuit description: this circuit has been designed to provide 3vin to 5vin boost to white leds at approximately 4v output at 1.5amps. high efficiency and 3-5volt input dictated the choice of the controller and external components. in order to reduce the reference voltage to a low 150mv and improve efficiency, an additional ic op amp (lmv321) was used to amplify the reference to 1.2v feedback voltage. the sp6121 is the synchronous buck controller that is being used as a buck/boost dc/dc controller. a p-channel mosfet and n-channel mosfet are used for higher efficiency in this synchronous sepic buck-boost configuration. the high switching frequency (500 khz) allows the use of small, mutually-coupled 4.7uh inductors. this report includes the application schematic complete with component part numbers and figures 1-11 illustrating electrical performance of the design.
design solution 20 mar29-06 sp6121 buck/boost circuit fo r led driver up to 1.5a copyright ?2006 page 2 of 4 sipex corporation led efficiency vs input voltage 50 60 70 80 90 100 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 input voltage (v) efficiency (%) iout=1.0a iout=1.5a input current vs input voltage 0.5 1.0 1.5 2.0 2.5 3.0 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 input voltage (v) input current (a) iout=1.5a iout=1.0a figure 1. efficiency graph figure 2. input current graph figure 3. switching behaviors figure 4. switching behaviors figure 5. switch node figure 6. switch node vin=5v, iout=1.5a i l2 1a/div pdrv ndrv i l1 1a/div vin=3.3v, iout=1.5a i l2 1a/div pdrv ndrv i l1 1a/div vin=5.0v, iout=1.5a primary p fet secondary n fet vin=3.3v, iout=1.5a primary p fet secondary n fet
design solution 20 mar29-06 sp6121 buck/boost circuit fo r led driver up to 1.5a copyright ?2006 page 3 of 4 sipex corporation figure 9. start up figure 10. start up vin=5v, iout=1.5a vin=3.3 v, iout=1.5a figure 8. ripple noise vin=3.3v, iout=1.5a figure 7. ripple noise vin=5.0v, iout=1.5a vref vout vin vref vout vin iin 1a/div vref vout vin iin 1a/div vref vout vin
design solution 20 mar29-06 sp6121 buck/boost circuit fo r led driver up to 1.5a copyright ?2006 page 4 of 4 sipex corporation 4.7uh r3 545 ohm c1 2.2uf rref 0.1 ohm u1 sp6121 1 2 7 6 5 4 3 8 vcc gnd ndrv iset isense comp vfb pdrv d2 5.1v c1 10uf l1l2 (744870004) wurth electronic c2 1uf d1 luxeon lmv321 1 3 4 + - out cout 100uf l1 vin 3.0v-5.0 v r2 4k 4.7uh q1 fds6375 r4 10k vfb=1.25v gain=1+r2/r3 i led=vref /0.1ohm =150mv/0.1ohm r1 10ohm vout vref 2 l2 c3 1uf cin 47uf q2 fdn337n 5 figure 11. application schematic
rev 7/25/01 features description the sp6121 demo board is designed to help the user evaluate the performance of the sp6121 for use in a distributed power system. the sp6121 operates over an input voltage range of 3.0v to 7.0v, and can deliver efficiencies as high as 95%. the sp6121 demo board is a complete power supply ready for use in applications where high stability, excellent transient response, high efficiency and power density are critical concerns. the demo board, a completely assembled and tested pcb with surface mount components, has been designed as a sip board that can be vertically mounted in an existing application. dc/dc synchronous buck converter for distributed power systems. sip design provides complete, ready to use solutions for : vin=3.0 - 7.0v vout=1.25 - 5.0v i out=8.0a (no air flow required). high efficiency: 86 to 95% excellent transient response small size: 550x2500mils, vertical mounting power good output sp6121 demo board manual
rev 7/25/01 2 board schematic and layout the sp6121 demo board is configured as a highly efficient, synchronous dc/dc buck converter. it has been optimized to deliver excellent thermal and emi performance. figure 1. sp6121 demo board ? layer 1, top view. figure 2. sp6121 demo board, layer 4, top view. the sp6121 demo board has four, 2 oz copper layers that provide improved noise immunity and minimize power losses. components are placed on the top and bottom sides of the pcb as shown on figures 1and 2. the row of pads (1 to 11) at the edge of the board is designed for solderable pins such as the nas interplex forked pins (17 x 42 mil cross section). pin connections to the demo board circuit are indicated in figure 3. (pad 11 is a no connect.)
rev 7/25/01 3 figure 3. sp6121 demo board schematic. demo board component selection the input capacitor, c6 , can be either a ceramic or tantalum capacitor. its choice depends on the user?s system input voltage transient. if the highest possible efficiency is required, a ceramic 47uf capacitor is recommended. the demo board circuit includes a schottky diode, d1, across the low side switch. it prevents q2?s internal body diode from turning on and dissipating power during the nonoverlap time when both q1 and q2 are off. at a 500khz switching frequency, these losses would decrease overall efficiency by 0.5 ? 0.6%. the output voltage is set by the resistor divider: r3/r4. the output voltage is calculated using the following: ref out v r r v + = 1 4 3 , where v ref = 1.25v. for the sp6121 demo board where v out = 2.5v. choosing r4 equal to 10k, then k r r 10 4 3 = = the considerations, tradeoffs and calculations required to select the power mosfets (q 1 , q 2 ), the inductor (l 1 ), the input and output capacitors (c 1 , and c6, c 8 , and c 9 , l1 1.6uh c1 2.2uf 10 po wer ok u1 sp6121 1 2 7 6 5 4 3 8 vcc gnd ndrv iset isense comp vfb pdrv gnd c7 0.1uf u2 sp708 4 6 7 5 1 2 8 3 vcc pfi pfo gnd reset res et nc mr vin 9 c11 56pf 1,2,3,4 c9 470uf c8 470uf r4 10k trim c6 47uf d1 r2 2.3k r3 10k v out ceramic 7,8 r1 10k c2 56pf q2 fds6690a r5 10k c3 3.9nf r6 5.0 q1 fds6375 c10 0.1uf 5,6 c5 1.0uf +3.0v-7.0 v 2.5v
rev 7/25/01 4 respectively), and the current set resistor (r 2 ), are discussed in detail in the sp6121 data sheet. using the demo board to use the demo board, connect the input voltage, v in to pins 7 and 8 and a ground, gnd, to pins 5 and 6. connect the load to pins 1, 2, 3, and 4. pin 9 provides a logic level ?power good? signal and pin 10 is used for trimming the output voltage. when measuring efficiency, care must be taken to keep leads between measuring devices, the power supply (v in ) and the demo board as short as possible and the measurement probes should be connected to pins 4 (v out ) and 7 (v in ). the sp708 power management controller ic (u 2 ) on the demo board is used to generate a power good signal. on this demo board, when the voltage on the pin 6 (pfi) of u2 is 1.25v or less, u2?s pin 7 (pfo) goes low. pin 6 can be connected directly, or through a resistor divider, to v out or v in . demo board characteristics figure 4. efficiency vs. i load. vout=2,5v figure 5. line regulation. vout=2.5v -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 3456 vin (v) vout tolerance (%) i load=5.0a i load=3.0a 78 80 82 84 86 88 90 92 94 96 012345678910 i load (a) efficiency (%) c6=47uf, 3.3/2.5v c6=47uf,5.0/1.9v c6=330uf,3.3/2.5v c6=330uf,5.0/1.9v
rev 7/25/01 5 figure 6. load regulation. vout=2.5v figure 7. load step response. i load step 0.4a to 6.0a. ch1-vout; ch4-i load. vin=5.0v, vout=2.5v figure 8. output ripple. vin=5.0v,vout=2.5v, iload=6.0a -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 02468 i load (a) v out tolerance (%) vin=3.3v vin=5.0v
rev 7/25/01 6 demo board recommended parts: no. qty part manuf. manuf. p/n / package 1 1 c1 capacitor ceramic 2.2uf/16v/x7r/10% any approved package 1206 2 2 c2,c11 capacitor ceramic 56pf/50v/x7r/10% "-" 603 3 1 c3 capacitor ceramic 3.9nf/50v/x7r/10% "-" 805 4 1 c5 capacitor ceramic 1uf/16v/x7r/10% "-" 603 5 1 c6 capacitor tantalum 220uf/10v/10% "-" 7343 or or capacitor tantalum 330uf/10v/20% capacitor ceramic 47uf/x7r/10v/10% "-" ?-? 1812 7343 6 2 c7,c10 capacitor ceramic 0.1uf/16v/x7r/10% "-" 603 7 2 c8,c9 capacitor tantalum 470uf/10v/10% "-" 7343 8 1 d1 diode schottky 30v/2.0a "-" package do-214aa 9 1 l1 inductor 1.6uh/15a/3.3 mohm panasonic etq-p6f1r6sfa 10 1 q1 p-mosfet 20v/8.0a/32mohm fairchild fds6375/ so-8 11 1 q2 n_mosfet 30v/13a/10mohm fairchild fds6690a/ so-8 12 2 r1,r5 resistor 10k/63mw/5% any appoved package 603 13 1 r2 resistor 2.1k/63mw/5% "-" 603 14 2 r4,r3 resistor 10k/63mw/1% "-" 603 15 1 r6 resistor 10 ohm/0.63mw/5% "-" 603 16 1 u1 synch. buck controller sipex sp6121/so-8 17 1 u2 low power microprocessor sipex sp708/ usoic-8 supervisory circuits 18 11 pins 17x42 mils cross section nas interplex
sp6128a reliability report page 1 of 4 reliability and qualification report silan bc1 process reliability qualification using the sp6128a prepared by: salvador wu & greg west reviewed by: fred claussen qa engineering vp quality & reliability date: january 2, 2007 date: january 2, 2007
sp6128a reliability report page 2 of 4 table of contents title page 1 table of contents 2 device description 2 pin out 2 manufacturing information 2 package information 2 reliability test summary 3 life test data 3 fit data calculations 4 mtbf data calculations 4 esd testing 4 latch-up testing 4 14l tssop pb free package qualification addendum 4 device description : the sp6128a is a fixed frequency, voltage m ode, synchronous pwm controller designed to work from a single 5v or 3.3v input supply, providing excel lent ac and dc regulation for high efficiency power c onversion. requiring only few external components, the sp6128a packaged in a 14-pi n tssop, is especially suited for low voltage applications where cost, small size and high efficiency are critical. the operating frequency is internally set to 300khz, allo wing small inductor values and minimizing pc board space. the sp6128a drives two n-channel power mosfets for improved efficiency and includes an accurate 0.8v refe rence for low output voltage applications. manufacturing information : product: sp6128a description: low voltage sync. buck controller mask set(s): ms1236 lot number(s): cf10190.1, cf10191.1, cf10192.1 process: sil-bc1 wafer fab: silan package information : package type: 14 pin tssop package code: jedec pin out sp6128a
sp6128a reliability report page 3 of 4 reliability qualification test summary: stress level device lot numbe r burn-in temp sample size no. fail 168hrs sp6128a cf10190.1 125 c 77 0 168hrs sp6128a cf10191.1 125 c 77 0 168hrs sp6128a cf10192.1 125 c 77 0 1000hrs sp6128a cf10190.1 125 c 77 0 1000hrs sp6128a cf10191.1 125 c 77 0 1000hrs sp6128a cf10192.1 125 c 77 0 life test life testing is conducted to determine if th ere are any fundamental reliability related failure mechanism(s) present in the device. these failure mechanisms can be divided roughly into four groups: 1. process or die related failures such as oxide defects, metallization defects, and diffusion defects. 2. assembly related failures such as chip mount defects, wire bond defects, molding defects, and trim/for m/singulation defects. 3. design related defects. 4. miscellaneous, undetermined, or application induced failures. 125c operating life test results as part of the sipex design qualification program, the product/reliability engineering group subjected 231 parts to 168 hours of 125 c life stress testing and then to 1000 hours of 125 c life stress testing. 168 hour timepoint the 231 parts were subjected to the life test profile and completed the first phase with no failures. 1000 hour timepoint 231 parts were reintroduced to life stre ss testing, completing the 1000 hour htol time point without any failures or significant shifts in process parameters. fit rate calculations fit rate (failures in time) is the predicted number of fa ilures per billion device hours. this predicted value is based upon, ? the life test conditions summarized in th e htol table (time/temperature, device quantity, failure quantity). ? the activation energy (e a ) for potential failure modes. the weighted activation energy(e a ) of observed failure mechanisms for sipex products has been determined to be 0.8ev.
sp6128a reliability report page 4 of 4 based on the above criteria sp6128a product fit rates for 25 , 55 , and 70 c of operation at 60% and 90% confidence levels have been calculated and listed below. fit failure rates: sp6128a bc1 silan process confidence level +25 c +55 c +70 c 60% 2.4 35.3 113.2 90% 6.3 90.6 290.3 1 fit = 1 failure per billion device-hours mtbf calculation: sp6128a bc1 silan process confidence level +25 c +55 c +70 c 60% 4.09e+08 2.83e+07 8.83e+06 90% 1.60e+08 1.10e+07 3.44e+06 esd testing human body model esd ? 77 units were subjected to human body model esd testing at +/- 2kv. all units passed. latch-up testing jed-std latch-up testing 85c - 77 units from the qualification lot were subjected to jed-std latch-up testing at 85c. all units passed at +/-200ma. additional reliability tests 77 of the units were placed on -65c/+150c temperat ure cycle testing, 77 of the units were placed on highly-accelerated temp. and humidity stress testing (130c, 85% rh), 200 of the units were placed on elfr testing and 77 on -65c/+150c thermal shock testing. all units passed testing as summarized in the following table. test condition time sample size # of rejects temp. cycles -65 c/+ 150 c 1000 cycles 77 0 hast unbiased 130 c/ 85%rh 96hrs 77 0 elfr 125c 48hrs 200 0 thermal shock -65c/+150c 500 cycles 77 0

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